WisIOE W7500P development board

WIZnet released the world's first IOP (Network Offload Processor) W7500P chip, embedded ARM Cortex-M0 and hardware TCP/IP protocol stack, aiming to enter the IoT market. The W7500P and W7500 development board are designed for the ARM mbed platform and Arduino. The W7500P is a single-chip network offload processor (IOP). It not only embeds the ARM Coretex-M0 core with 128KB Flash, but also includes the full hardware TCP/IP stack core and PHY. Therefore, it is applicable to all kinds of embedded application platforms. Especially in the field of Internet of Things.

It integrates the TCP/IP protocol stack core of Ethernet MAC, supports TCP, UDP, IPv4, ICMP, ARP, IGMP and PPPoE protocols, has been tested by the market and is widely recognized. The W7500P is especially suitable for users who need a network connection in their application.

ARM Cortex-M0

• Maximum clock frequency 48MHz

Full hardware TCP/IP core

• 8 sockets
• Each socket has a maximum of 32KBSRAM
• MII (media independent interface)

RAM

• Flash: 128KB
• SRAM: 16KB to 48KB (such as 32KB socket cache is used, the minimum available 16KB, if the socket cache is not used, the maximum available 48KB)

Clock, reset and supply management

• POR (power-on reset)
• Voltage regulator: 3.3V to 1.5V
• 8 to 24MHz external crystal oscillator
• Internal internal 8MHz RC oscillator
• Phase-locked loop for CPU clock

ADC

• 12bit, 8ch, 1Msps

DMA

• 6 DMA controller
• Peripherals: UARTs, SPIs

GPIO

• 53 I/Os (16 IO x 3ea, 5 IO x 1ea)

Debugging mode

• Serial Debug (SWD)

Timer/PWM

• Watchdog*1 (32-bit subtraction counter)
• Timer*4 (32-bit or 16-bit subtraction counter)
• PWM*8 (32 counter/timer with 6-bit programmable prescaler)

Communication Interface

• 3 UART (2 UART FIFO and flow control, 1 simple UART)
• 2 SPI
• 2 I2C (master/slave, fast mode (400 Kbps))

Encryption

• 1 RNG (random number generator): 32-bit random number

Package

• 64 TQFP (7 × 7 mm)